Depending on the applications, high standards may be placed on chip packages for electronic components and electronic elements. Such requirements may include the need for the chip package to exhibit stability, protection against radiation and isolation capabilities. The capability of today's semiconductor chips are limited by efficiency of heat dissipation across the chip package and from the chip package during operation. This may be a result of increasing circuit integrations density and circuit performance, and increasing area-related density, e.g. packing per area. As a result higher thermal loads may be placed on the circuit components. Junction temperatures in current chips may normally be limited to about 150° C. to 200° C. to ensure reliability of the chip package. Current and/or switching frequency may have to be limited, e.g. reduced, to ensure that these temperatures may not be exceeded.
Semiconductor elements or integrated circuits may normally be arranged in enclosed chip housings, to protect them from the external environment during operations. Today's concepts are primarily based on hybrid package construction, through which, the realization of at least two interfaces may be necessary. The first interface, referred to as a chip housing interface, may traditionally be produced by chip manufacturers, wherein complex connection techniques, e.g. wire or flip chip bonding may be used. The second interface may include an interface between the chip housing and the board/module, and may normally be realized by the end-user.
Non-hermetic packages, from plastic or ceramic-based, may meanwhile, be unsuitable for many applications in semiconductor technology, as they may not be sufficient for protecting the electronic chip against external environmental influences, e.g. humidity, radiation, heat. Particularly, due to intensive humidity absorption, these packages may encounter challenges, for example, with respect to reflow solder, or cracking or fracturing through the popcorn-effect, therefore affecting its long term stability.
In order to protect the components from malfunctions or destruction caused by overheating, more measures for cooling of the components may be carried out by the user. Passive and even active methods may be used, which may be extremely challenging, with respect to expenditure, cost and efficiency. In order to reduce cost and expenditure, variable process techniques from the chip manufacturers may be provided, which may minimize thermal load of the components. Conventional methods provide a reduction in the thermal mass of silicon chips, by which, the thickness of the chips, may be reduced, for example by thinning methods, such as grinding or etching. Additionally, effective heat sinks may be integrated on chip level, e.g. using thick metallization. These methods introduce further challenges. The effective thinning of the semiconductor components during preparation may require specially techniques and sophisticated preparation methods. Thick metal layers may lead to a significant mechanical and thermal stress, and to destruction of the components due to the different thermal expansion coefficient between the chip, e.g. silicon, and the metal layers, e.g. Cu, at high temperatures which may be reached during pre-assembly and/or during operation of the chip. Therefore, in most cases, the power semiconductors may only be operated in areas, wherein the heat may not accumulate, to avoid thermal destruction of the chips. The efficiency may therefore be significantly reduced.
Passive cooling solutions, e.g. through use of lead frames, pose a large challenge. Due to the increasing integration density of components, and decreasing pitch distance, the preparation techniques costs and the requirements of solder paste and screen printing are greatly increased. An active cooling may normally, only be realized in the form of an externally attached or glued cooling body, e.g. holding cooling fluids, which may result in a largely reduced efficiency due to the successive insulation interfaces between cooling body and chip housing and between the chip housing and chip. The cost for an efficient chip package may account for more than 90% of the total manufacturing costs, due to the additional integration of appropriate isolations and cooling components.